Present memory devices such as synchronous dynamic random access memory (SDRAM) devices typically contain multiple memory banks in which each memory bank includes an internal bank controller and a corresponding independent block of memory, e.g., SDRAM memory. Often multiple requesters (e.g., microprocessors, direct memory access devices, etc.) are configured to access the same memory device. The memory banks share a common external interface having a data buss, an address buss, and a control buss, which enables access of the memory banks by the multiple requesters. In conventional systems, a single external controller is coupled between the memory requesters and the memory device to manage the access of the memory device by the requesters such that conflicts do not occur on the busses or within the memory device.
To access the memory device, one or more of the memory requesters generates a memory request requesting access to specified memory banks within the memory device. The external controller receives the requests and selects one request at a time to access the memory device. The external controller then executes a control sequence that connects with the appropriate internal bank controller of the memory bank identified in the selected request and begins a cycle of activating the memory bank, loading the memory address, and transferring a burst of data to or from the memory block of the activated memory bank. Depending upon the direction of the transfer, data is passed either from the memory device to the requester (i.e., read from the memory device) or from the requester to the memory device (i.e., written to the memory device).
The external controller activates only one of the multiple memory banks at a time, referred to herein as the “active” bank. During each activation, the external controller either issues a read command to read data from the active bank or a write command to write data to the active bank. Typically, the remaining “non-active” banks “refresh” and/or “precharge” during the time when another memory bank is active. The amount of time used to refresh and precharge these memory banks, however, is typically much less than the amount of time available for such activities. Thus, the memory banks as a whole are underutilized. In addition, depending on the amount of data being transferred during each data exchange with the memory device, one or more of the data, address, and command busses are often underutilized as well.
There is an ever-present need to improve the bandwidth and latency of memory systems. The inventor has recognized that improvements in bandwidth and latency are achievable by more fully using the existing underutilized memory bank and buss resources. The present invention fulfils the need for improved bandwidth and latency of memory systems among others.